1. Field
One embodiment of the invention relates to a maximum likelihood and a decoding method therefor used in an optical disk device which reproduces information on an optical disk, a hard disk device which reproduces information on a hard disk, a communication apparatus which reproduces received information received from a communication/transmission path, and the like.
2. Description of the Related Art
In recent years, optical disk devices such as a DVD (Digital Versatile Disk) player have been widely popularized. Various schemes have been researched and developed, and commercially manufactured. In particular, also in the field of optical recording/reproduction, high-density recording is advanced, and a linear recording density considerably increases. Furthermore, a laser wavelength becomes short, and a numerical aperture of a lens increases. For this reason, the quality of the reproduced signal quality is greatly reduced due to tilt. Therefore, as a countermeasure against this drawback, a PRML (Partial Response and Maximum Likelihood) signal processing scheme is popularly applied.
In a conventional DVD system, a binarizing scheme for a reproduced signal, a waveform slice scheme is employed. In the waveform slice scheme, binarization is performed depending on whether an amplitude of a reproduced signal is higher or lower than a threshold value. However, since the amplitude of the reproduced signal decreases due to high-density recording, a large number of identifying errors occur in the binarization performed by the waveform slice. It is known that the PRML signal processing scheme can obtain a higher signal quality than that in a conventional level slice scheme, even in information recorded on an optical disk at a high density, therefore, the PRML signal processing scheme is also applied to an optical disk device using a blue laser beam.
In the PRML signal processing scheme, through an equalizer, an input signal is supplied to a Viterbi decoder, and a decoding signal is output from the Viterbi decoder. An equalization error signal generated by an input signal and a decoding signal is also supplied to a coefficient controller, and a coefficient of an equalizer is learning-controlled. The Viterbi decoder cumulatively sums errors between actual input signals at sample points and all supposed paths and selects a path having a minimum cumulative sum. A bit string corresponding to the selected path is output as a decoding signal.
With an increase in required multi-speed of reproduction or required data rate, a maximum likelihood decoder is required to achieve a high throughput. Since a throughput is in proportion to an operating frequency of a circuit, it may be considered to increase the operating frequency to increase the throughput. However, in a maximum likelihood decoder, branch metrics are calculated, and calculations for addition, comparison, and selection between the branch metrics and path metrics must be performed at a high speed. For this reason, even though the operating frequency is merely increased, the throughput cannot be easily increased. Therefore, as described in document 1 “A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder,” P. J. Black, et al., IEEE JSSC, Vol. 27, No. 12, December 1992, pp 1877-1885 and document 2 “A 210 Mb/s Radix-4 Bit-level Pipelined Viterbi Decoder,” A. K. Yeung, J. M. Rabaey, ISSCC 1995, pp 88-89, 344, Table 1, a method called radix-4 in which the number of elements of an ACS (Addition, Comparison, Selection) calculation circuit is increased by applying the graph algorithm to decrease the operating rate of the circuit to ½ while keeping a throughput is proposed.
In order to cope with a Blu-ray disk (trademark) which is required to achieve a higher throughput, a maximum likelihood decoder using a method called Radix-16 which further reduces (⅛) an operating speed is reported in document 3 “Reconfigurable Front-End System For BD/DVD/CD Recorder,” G. S. Choi, IEEE Transactions on Consumer Electronics, Vol. 53, No. 2, May 2007, pp 474-480.
However, although an operating speed can be reduced in the radix-4 or radix-16, an ACS circuit scale disadvantageously increases. Comparison between radix-2 and the radix-4 is shown in Table 1 of document 2. In contrast to a throughput of 50 Mbps in the radix-2, a throughput increases to 140 Mbps in the radix-4. However, in the radix-4, an area of an ACS circuit also increases from 7.1 mm2 (design rule is 2.0 μm) to 33.6 mm2 (design rule is 1.2 μm).
In general, a semiconductor inevitably has a leakage current, a leakage current generated due to only the presence of a circuit of 90-nm generation, 65-nm generation, or later the micropatterning of which advances cannot be neglected.
In listening to music on a CD or in viewing of a moving image on a DVD by using a maximum likelihood decoder using the radix-4 or radix-16 to reduce an operating speed as described above, electric power may be consumed in an arithmetic unit or a storage unit having a circuit scale which increases regardless of a low required throughput. Even in reproduction of disks of the same type, the disks may be reproduced at various speeds depending on the states of the disks, and required throughputs may change. The change in throughput may occur in not only reproduction of an optical disk but also a maximum likelihood decoder used in a hard disk device in which data is reproduced at a dual speed (rotating speed changes) or a communication system. More specifically, in a low-throughput state with which a radix-2 circuit can normally cope, the arithmetic unit or the storage unit the scale of which increases is consequently useless. Electric power is therefore also consumed even in this useless circuit.
Various countermeasures which reduce the power consumption in a decoding apparatus operating at a high speed are described in Jpn. Pat. Appln. KOKAI Publication Nos. 2007-273016 (FIG. 1) and 2006-4465 (FIG. 1). However, none of the countermeasures can realize an appropriate compromise between throughput and power consumption.
On the other hand, in the radix-4, 2-bit data must be simultaneously input to an ACS circuit to reduce an operating frequency by half. For this reason, 1-bit serial data must be converted into 2-bit serial data by using a serial/parallel converter such as a flop-flop, a latency in a circuit increases, and a response speed of the circuit decreases. As described above, an equalization error signal is supplied to a coefficient controller, and a coefficient of an equalizer is feedback-controlled. When the waveform of data is shaped, decoding performance is not influenced even though a response speed is low. However, when the waveform of data considerably changes due to scratches and stains on a disk, decoding performance is deteriorated with an increase in latency. In this manner, when a high throughput is realized, decoding performance is deteriorated.
As described above, in a conventional maximum likelihood decoder which is increased in circuit scale to realize a high throughput, the electric power consumed in arithmetic units the number of which increases cannot be neglected at a low throughput, and a problem is posed in terms of power consumption. Another problem is also posed in that, in order to realize a high throughput, a latency increases and decoding performance is deteriorated.